The present invention relates to a microcomputer incorporating a memory. More particularly, this invention relates to a microcomputer in which power consumption can be reduced by varying a memory access time according to the situation and a memory access control method by the use of a built-in micro processor (CPU).
Explanation will be made below on a conventional microcomputer incorporating a memory therein. In recent years, with a rapid growth in, for example, portable information equipment (such as a cordless telephone or a Personal Handyphone Systems) or digital information household electrical appliances, high-speed and low power consumption microcomputers are required. However, achievement of a higher operating speed needs an increase in capacity of the built-in in memory, with an attendant problem of an increase in power consumption.
Consequently, operation of the on-board microcomputer is stopped or performed at a low speed in the aforementioned information equipment or household electrical appliances according to the situation, so as to achieve high-speed operation during normal operation and reduce power consumption.
Specifically, a digital camera requires a microcomputer of high performance since after taking a photograph the image is compressed by a data compressing system such as JPEG (Joint Photographic Experts Group). At the same time, power consumption must be reduced since such a camera is normally driven by a cell or battery.
Therefore, in the digital camera, the microcomputer is operated at a high speed immediately after a shutter is pressed, or during display of an image, or the like where high-speed operation is needed. On the contrary, for example, when the shutter is not pressed, that is, when the high-speed operation is not needed, the power source of the on-board microcomputer (or the built-in microprocessor) is turned off or the speed of an operation clock of the microcomputer (or the built-in microprocessor) is reduced, thereby reducing the power consumption.
However, in the case where the power consumption is reduced in the same manner as in the conventional microcomputer, another microcomputer (or another microprocessor) for performing management of the power source or the clock is required to be housed inside the information equipment or household electrical appliances. Namely, turning off the power source and reduction in the speed of the operation clock, so as to reduce the power consumption of the equipment as a whole must be performed under the control of this managing microcomputer.
Furthermore, the above-described managing microcomputer must not only vary the frequency of the operation clock per se but also vary the frequency multiplication ratio of the other microcomputer (other than the managing microcomputer) or divide the frequency, so as to decrease the speed of the operation, thereby reducing the power consumption.
In this way, in the case where the power consumption is reduced by the conventional method, a managing microcomputer is required to be provided in each of the equipment or appliances. This increases the number of component parts resulting into a problem that miniaturization cannot be achieved. Moreover, in the case where the speed of the clock for operating the processor is controlled, a time is taken to stabilize the oscillating frequency of an oscillator, resulting in complicated control.
Additionally, for example, in the case where a waiting operation is performed, namely, transition to the waiting state is caused by a loop according to an instruction from the CPU, a cache memory inside the microcomputer is hit, thereby inducing an increase in power consumption of the cache memory.
The present invention has been accomplished in light of the problems described above. It is an object of the present invention to provide a microcomputer capable of achieving low power consumption by utilizing access control to a built-in memory without controlling a power source and an oscillator, and a memory access control method by the built-in processor.
In order to solve the above-described problems and achieve the above-described object, a microcomputer according to a first aspect of the present invention includes a CPU, a memory and a memory controller. The memory controller performs access control to the memory in response to a memory access request from the CPU. Furthermore, the microcomputer comprises a storage unit for storing a waiting period relating to memory access. The memory controller reads this waiting period upon receipt of the memory access request, and then, performs the access control to the memory after a lapse of the waiting period.
Thus, the waiting period can be set in, for example, the counter based on the set value (the waiting period) of the storage unit before the memory access control by the memory controller. The transition from the waiting state to the access state is effected upon completion of the count-down of the counter, so that the CPU can be operated at a low speed.
Further, operation clock of the CPU may be stopped during the waiting period. Consequently, for example, when the waiting flag is active, the operating clock of the CPU is stopped, so that the clock is operated in the waiting state, and therefore, circuits such as a latch, a flip-flop and a clock driver cannot consume electric power. Thus, it is possible to produce an effect of reducing power consumption with more efficiency.
Further, the storage unit may independently store a waiting period in the case where the memory access is performed in response to the request from the CPU and a waiting period in the case where the memory access is performed in response to the request from an external device. In such a case, the memory controller can accept not only the memory access request from the CPU but also the memory access request from the external device. Buses are adjusted based on the precedence of the memory access requests when these requests are competed with each other, so that access to the memory is obtained after a lapse of one of the waiting periods selected according to the adjustment.
Thus, the microcomputer comprises the storage unit for independently storing the waiting periods according to the CPU and the external device. Further, a unit for assigning priorities to the memory access requests and selecting the waiting period according to the memory access request having the higher priority, so as to perform the processing according to the device sending the memory access request.
According to a second aspect of the present invention, a memory access control method comprises a step of storing a waiting period relating to memory access and a step of reading the waiting period upon receipt of the memory access request in the memory controller so as to perform the access control to the memory after a lapse of the waiting period.
According to the second aspect of the present invention, the waiting period set in the storing step is set in, for example, the counter before the memory access control by the memory controller. In the control step, the transition from the waiting state to the access states is effected upon completion of the count-down of the counter, so that the CPU can be operated at a low speed.
Further, operation clock of the CPU may be stopped during the waiting period. Consequently, for example, when the waiting flag is active, the operating clock of the CPU is stopped, so that the clock is operated in the waiting state, and therefore, circuits such as a latch, a flip-flop and a clock driver cannot consume electric power.
Further, a waiting period in the case where the memory access is performed in response to the request from the CPU and a waiting period in the case where the memory access is performed in response to the request from external device may be independently stored in the storing step, and not only the memory access request from the CPU but also the memory access request from the external device can be accepted in the control step, in which buses are adjusted based on the precedence of the memory access requests when these requests are competed with each other, so that access to the memory is obtained after a lapse of one of the waiting periods selected according to the adjustment.
Thus, the memory access control method comprises the steps of independently storing the waiting periods according to the CPU and the external device, and assigning priorities to the memory access requests and selecting the waiting period according to the memory access request having the higher priority, so as to perform the processing according to the device sending the memory access request.